The invention generally relates to an optical display device, such as a silicon light modulator (SLM), for example.
Referring to FIG. 1, a silicon light modulator (SLM) 1 may include an array of LCD pixel cells 25 (arranged in rows and columns) that form corresponding pixels of an image. To accomplish this, each pixel cell 25 typically receives an analog voltage that controls the optical response of the pixel cell 25 and thus, controls the perceived intensity of the corresponding pixel. If the pixel cell 25 is a reflective pixel cell, the level of the voltage controls the amount of light that is reflected by the pixel cell 25, and if the pixel cell 25 is a transmissive pixel cell, the level of the voltage controls the amount of light that passes through the pixel cell 25.
There are many applications that may use the SLM 1. For example, a color projection display system may use three of the SLMs 1 to modulate red, green and blue light beams, respectively, to produce a projected multicolor composite image. As another example, a display screen for a laptop computer may include an SLM 1 along with red, green and blue color filters that are selectively mounted over the pixel cells to produce a multicolor composite image.
Regardless of the use of SLM 1, updates are continually made to the SLM cells 20 to refresh or update the displayed image. More particularly, each pixel cell 25 may be part of a different SLM cell 20 (an SLM cell 20a, for example), a circuit that includes the pixel cell 25 and typically includes a capacitor 24 that stores a charge to maintain the appropriate voltage on the pixel cell 25. The SLM cells 20 typically are arranged in a rectangular array 6 of rows and columns.
The charges that are stored by the SLM cells 20 typically are updated (via row 4 and column 3 decoders) in a procedure called a raster scan. The raster scan is sequential in nature, a designation that implies the SLM cells 20 of a row are updated in a particular order such as from left-to-right or from right-to-left.
As an example, a particular raster scan may include a left-to-right and top-to-bottom “zig-zag” scan of the array 6. More particularly, the SLM cells 20 may be updated one at a time, beginning with the SLM cell 20a that is located closest to the upper left corner of the array 6 (as shown in FIG. 1). During the raster scan, the SLM cells 20 are sequentially selected (for charge storage) in a left-to-right direction across each row, and the updated charge is stored in each SLM cell 20 when the SLM cell 20 is selected. After each row is scanned, the raster scan advances to the leftmost SLM cell 20 in the next row immediately below the previously scanned row.
During the raster scan, the selection of a particular SLM cell 20 may include activating a particular word, or row, line 14 and a particular bit, or column, line 16, as the rows of the SLM cells 20 are associated with row lines 14 (row line 14a, as an example), and the columns of the SLM cells 20 are associated with column lines 16 (column line 16a, as an example). Thus, each selected row line 14 and column line 16 pair uniquely addresses, or selects, a SLM cell 20 for purposes of transferring a charge (in the form of a voltage) from a signal input line 12 to the capacitor 24 of the selected SLM cell 20.
As an example, for the SLM cell 20a that is located at pixel position (0,0) (in cartesian coordinates), a voltage that indicates a new charge that is to be stored in the SLM cell 20a may be applied to one of the video signal input lines 12. To transfer this voltage to the SLM cell 20a, the row decoder 4 may assert (drive high, for example) a row select signal (called ROW0) on a row line 14a that is associated with the SLM cell 20a, and the column decoder 3 may assert a column select signal (called COL0) on column line 16a that is also associated with the SLM cell 20a. In this manner, the assertion of the ROW0 signal may cause a transistor 22 (of the SLM cell 20a) to couple a capacitor 24 (of the SLM cell 20a) to the column line 16a, and the assertion of the COL0 signal may cause a transistor 18 to couple the video signal input line 12 to the column line 16a. As a result of these connections, the voltage of the video signal input line 12 is transferred to the capacitor 24. The other SLM cells 20 may be selected for charge updates in a similar manner.
Typically, there are two types of charge updates: a frame update is used to update the intensities of the pixel cells 25 for a new frame of the displayed image and a refresh update is used to maintain the charge that is stored on the capacitor 24 between frame updates. Without the refresh updates, the pixels intensities may fade due to charge leakage and/or charge sharing.
Because the array 6 might be quite large, the number of signal lines 12 typically is considerably smaller than the number of column lines 16. Therefore, the signal lines 12 typically are used to sequentially access the SLM cells 20 K cells at a time (where “K” represents the number of signal lines and typically is less than the number (M) of columns) [at a time] by activating the appropriate transistors 18. Because only K bit lines 16 are driven with new values (and thus, only K transistors 18 are activated), the remaining column lines 16 are in a tri-state condition and are coupled to the nonselected capacitors 24 of the row. Therefore, charge sharing typically occurs between the capacitors 24 and the tri-stated column lines 16.
One way to minimize the effect of the charge sharing is through the refresh updates. Another way to minimize the effect of charge sharing is to ensure that each capacitor 24 has a large capacitance. However, large capacitances typically imply large capacitors that occupy a substantial amount of the silicon on which the SLM cell 20 is fabricated, leaving little space for other circuitry of the SLM cell 20.
Thus, there is a continuing need for an arrangement that addresses one or more of the problems that are stated above.